1. Field of the Invention
The invention relates to a relay-race FLL/PLL high-speed timing acquisition device, and in particular to a relay-race FLL/PLL high-speed timing acquisition device having a frequency delimiter.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a non-independent continuous dual FLL/PLL high-speed timing acquisition device 1 according to the prior art. This non-independent continuous dual FLL/PLL high-speed timing acquisition device 1 comprises a voltage controlled oscillator 10, a phase detector 11, a frequency detector 12, a first loop filter 13, a second loop filter 14 and an adder 15. Since there is an interaction between a PLL L1 consisting of the phase detector 11, first loop filter 13 and voltage controlled oscillator 10, and a FLL L2 consisting of the frequency detector 12, second loop filter 14 and voltage controlled oscillator 10, it is difficult to optimize the timing acquisition and phase-locking processes. Therefore, a disadvantage of the conventional FLL/PLL high-speed timing acquisition device is requiring longer time for timing acquisition. Furthermore, the stability of this conventional FLL/PLL device may be poor because of the interaction between the FLL and PLL. In general, the above-mentioned loops (that is, FLL and PLL) needs dedicated circuits to implement the FLL and PLL, respectively.
Now, referring to FIG. 2, a conventional reference-clock-based FLL/PLL high-speed timing acquisition device is shown. This conventional FLL/PLL device comprises a voltage controlled oscillator 20, a phase detector 21, a frequency detector 22, a first loop filter 23 and a second loop filter 24, wherein the CLKref is generated by a common quartz oscillator. Before the PLL-based timing recovery system operates the frequency of the voltage controlled oscillator is adjusted into a PLL capture range by the FLL. In order to decrease the interaction between the FLL and PLL, two identical voltage controlled oscillators may be employed such that the FLL will not be affected by the PLL. However, the FLL still affects the PLL tracking process. Similarly, the above-mentioned loops (that is, FLL and PLL) needs dedicated circuits to implement the FLL and PLL, respectively.
To avoid the interaction between the FLL and PLL, a frequency delimiter FLL/PLL device 3 according to the prior art is shown in FIG. 3a. This frequency delimiter FLL/PLL device 3 comprises a voltage controlled oscillator 30, a phase detector 31, a frequency delimiter 32, a first loop filter (a phase-locked loop filter)33, a second loop filter (a frequency-locked loop filter) 34 and an adder 35. In the frequency delimiter FLL/PLL device 3, there is a bandpass filter used to cut off the FLL subsystem. Therefore, the timing acquisition system is only dominated by the PLL in the final tuning process. In practice, since an abrupt stopband turn is impossible in a low-order bandpass filter, the timing recovery system merely dominated by the PLL cannot avoid the interaction of the FLL and PLL. Therefore, there is an obscure region between the operation bands of the FLL and PLL. As shown in FIG. 3b, there is a guard-band region Bg preferably existing between the frequency delimiter and the capture range of the PLL to avoid the interaction between the FLL and PLL. However, this guard-band region will increase acquisition time. Moreover, dedicated circuits are also needed to realize the FLL and PLL, respectively.
Referring to FIG. 4a, there is shown another conventional FLL/PLL device 4. This conventional FLL/PLL device 4 comprises a first circuit 41, a delimiter 42, a loop filter 43 of PLL, a first lowpass filter 44, a voltage controlled oscillator 45, multiplier 46, 47, and 48, and a transition detector 49. The above-mentioned first circuit 41 comprises a second lowpass filter and a phase shifter connected to the second lowpass filter. The product of the output signal from the delimiter 42 located on the upper arm and the output signal from the first lowpass filter 44 can be used to detect the frequency difference between an input signal r(t) and local oscillator signal. When the frequency difference between the input signal frequency f.sub.i and the local oscillator frequency f.sub.o is less than a predetermined frequency threshold value F.sub.th, the upper circuit of the conventional FLL/PLL device 4 is turned off. At this point, this conventional FLL/PLL device 4 functions as a PLL circuit. In the FLL/PLL device 4, an automatic frequency control and phase-locking function are completely separated to allow the signal acquisition range and closed-loop bandwidth parameters to be independently established. Therefore, the interaction between the FLL and PLL can be eliminated to enhance the timing acquisition range. However, there is an inherent disadvantage. That is, there exists two stable equilibrium points P.sub.1 and P.sub.2 at 90.degree. and 270.degree.. As a result, in a coherent digital communication system, if the carrier recovery circuit is phase-locked at 270.degree., the detected data will be inverted. Therefore, an indicator or corrector has to be equipped to invert the inverted digital signal.